****************************************************************************** ****************************************************************************** BIRD ID#: 100.1 ISSUE TITLE: Allow Analog-Only *-AMS Model Terminals REQUESTER: Ian Dodd, Mentor Graphics; Arpad Muranyi, Intel Corporation DATE SUBMITTED: November 28, 2005 DATE REVISED: DATE ACCEPTED BY IBIS OPEN FORUM: PENDING ****************************************************************************** ****************************************************************************** STATEMENT OF THE ISSUE: The IBIS specification currently assumes that the signal ports of [External Model]s and [External Circuit]s are purely digital when using the *-AMS modeling languages, and a special syntax using A/D and D/A converters is required when using (analog) SPICE models. There are situations in which it may be desirable to have the capability of defining purely analog terminals in *-AMS models to be used with IBIS through the [External Model] and [External Circuit] keywords. This BIRD describes a change to the IBIS specification through which the referencing of *-AMS models containing only analog terminals is allowed. ****************************************************************************** STATEMENT OF THE RESOLVED SPECIFICATIONS: The Language subparameter of the [External Model] and [External Circuit] keywords shall have two additional options, namely "VHDL-A(MS)" and "Verilog-A(MS)", in which the parentheses indicate that the model uses only analog terminals. When such references to the *-AMS languages are made in [External Model]s and [External Circuit]s, the requirements of using the A_to_D and D_to_A converters with SPICE models shall apply to the *-A(MS) models as well. Change the following sections in Section 6b: MAYBE: ====== In the section entiteled "LANGUAGES SUPPORTED" add Verilog-A(MS) and VHDL-A(MS) after the 4th paragraph and explain birefly that these are the same languages as Verilog-AMS and VHDL-AMS, except that analog only content??? and terminals are also allowed. REWRITE: ======== The "SPICE versus VHDL-AMS and VERILOG-AMS" section starting from it's 2nd paragraph. Change illustrations accordingly. Under the keywords [External Model], [End External Model], replace: | Language: | | Accepts "SPICE", "VHDL-AMS", or "Verilog-AMS" as arguments. | The Language subparameter is required and must appear only | once. with: | Language: | |* Accepts "SPICE", "VHDL-AMS", "Verilog-AMS", "VHDL-A(MS)" |* or "Verilog-A(MS)" as arguments. The Language subparameter | is required and must appear only once. In the same keyword section, under "Ports" change 2nd paragraph from: | Note that the user may connect | SPICE models to A_to_D and D_to_A converters using custom | names for analog ports within the model unit, so long as the | digital ports of the converters use the digital reserved port | names. to: | Note that the user may connect |* SPICE, Verilog-A(MS) and VHDL-A(MS) models to A_to_D and D_to_A converters using custom | names for analog ports within the model unit, so long as the | digital ports of the converters use the digital reserved port | names. Under section "Digital-to-Analog/Analog-to-Digital Conversions", replace: | These subparameters define all digital-to-analog and | analog-to-digital converters needed to properly connect | digital signals with the analog ports of referenced external | SPICE models. These subparameters must be used when [External | Model] references a file written in the SPICE language. They | are not permitted with Verilog-AMS or VHDL-AMS external files. with: | These subparameters define all digital-to-analog and | analog-to-digital converters needed to properly connect | digital signals with the analog ports of referenced external |* SPICE, Verilog-A(MS) or VHDL-A(MS) models. These subparameters must be used when [External |* Model] references a file written in the SPICE, Verilog-A(MS) or VHDL-A(MS) languages. They | are not permitted with Verilog-AMS or VHDL-AMS external files. Under section "D_to_A", replace: | As assumed in [Model], some interface ports of [External | Model] circuits expect digital input signals. As SPICE models | understand only analog signals, some conversion from digital | to analog format is required. with: | As assumed in [Model], some interface ports of [External |* Model] circuits expect digital input signals. As SPICE, Verilog-A(MS) or VHDL-A(MS) models | understand only analog signals, some conversion from digital | to analog format is required. A couple of paragraphs down in the same section also replace: | The port1 and port2 entries hold the SPICE analog | input port names across which voltages are specified. These with: |* The port1 and port2 entries hold the SPICE, Verilog-A(MS) or VHDL-A(MS) analog | input port names across which voltages are specified. These Under section "A_to_D", replace: | The A_to_D subparameter is used to generate a digital state | ('0', '1', or 'X') based on analog voltages generated by the | SPICE model or analog voltages present at the pad/pin. This | allows an analog signal from the external SPICE circuit or | pad/pin to be read as a digital signal by the simulation tool. with: | The A_to_D subparameter is used to generate a digital state | ('0', '1', or 'X') based on analog voltages generated by the |* SPICE, Verilog-A(MS) or VHDL-A(MS) model or analog voltages present at the pad/pin. This |* allows an analog signal from the external SPICE, Verilog-A(MS) or VHDL-A(MS) circuit or | pad/pin to be read as a digital signal by the simulation tool. Above Figure 7, replace: | Note that, while the port assignments and SPICE model must | be provided by the user, the D_to_A and A_to_D converters will | be provided automatically by the tool (the converter | parameters must still be declared by the user). There is no | need for the user to develop external SPICE code specifically | for these functions. | | A conceptual diagram of the port connections of a SPICE | [External Model] is shown below. with: |* Note that, while the port assignments and a SPICE, Verilog-A(MS) or VHDL-A(MS) model must | be provided by the user, the D_to_A and A_to_D converters will | be provided automatically by the tool (the converter | parameters must still be declared by the user). There is no |* need for the user to develop external SPICE, Verilog-A(MS) or VHDL-A(MS) code specifically | for these functions. | |* A conceptual diagram of the port connections of a SPICE, Verilog-A(MS) or VHDL-A(MS) | [External Model] is shown below. Change Figure 7 and its caption from: | +-------------+ | | | | +------------+ | |--- A_puref | | |>--- my_drive ---->| | | D_drive -->| D_to_A | | | | | |---- my_ref -------| |--- A_pdref | +------------+ | | | | | | +------------+ | [External |--- A_pcref | | |>--- my_enable --->| Model] | | D_enable -->| D_to_A | | using | | | |---- A_gcref ------| SPICE |--- A_gcref | +------------+ | | | | | | +------------+ | |--- A_signal | | |<--- my_receive --<| | | D_receive -<| A_to_D | | | | | |---- my_ref -------| |--- A_extref | +------------+ | | | A_gnd ---| | | +-------------+ | | Figure 7: Example of an [External Model] I/O buffer using SPICE to: | +--------------+ | | | | +------------+ | |--- A_puref | | |>--- my_drive ---->| | | D_drive -->| D_to_A | | | | | |---- my_ref -------| |--- A_pdref | +------------+ | | | | | | +------------+ | [External |--- A_pcref | | |>--- my_enable --->| Model] | | D_enable -->| D_to_A | | using | | | |---- A_gcref ------| SPICE, |--- A_gcref | +------------+ |Verilog-A(MS),| | | or | | +------------+ | VHDL-A(MS) |--- A_signal | | |<--- my_receive --<| | | D_receive -<| A_to_D | | | | | |---- my_ref -------| |--- A_extref | +------------+ | | | A_gnd ---| | | +--------------+ | | Figure 7: Example of an [External Model] I/O buffer using SPICE, Verilog-A(MS) or VHDL-A(MS) Under section "Pseudo-Differential Buffers", replace: | The D_to_A adapters used for SPICE files can be set up to | control ports on pseudo-differential buffers. If SPICE is | used as an external language, the [Diff Pin] vdiff | subparameter overrides the contents of vlow and vhigh under | A_to_D. | | IMPORTANT: For pseudo-differential buffers under [External | Model], the analog input response may only be measured at the | die pads. The [Diff Pin] parameter is required, and controls | both the polarity and the differential thresholds used to | determine the D_receive port response (the D_receive port will | follow the state of the non-inverting pin/pad as referenced | to the inverting pin/pad). For SPICE models, the A_to_D line | must name the A_signal port under either port1 or port2, as | with a single-ended buffer. with: |* The D_to_A adapters used for SPICE, Verilog-A(MS) or VHDL-A(MS) files can be set up to |* control ports on pseudo-differential buffers. If SPICE, Verilog-A(MS) or VHDL-A(MS) is | used as an external language, the [Diff Pin] vdiff | subparameter overrides the contents of vlow and vhigh under | A_to_D. | | IMPORTANT: For pseudo-differential buffers under [External | Model], the analog input response may only be measured at the | die pads. The [Diff Pin] parameter is required, and controls | both the polarity and the differential thresholds used to | determine the D_receive port response (the D_receive port will | follow the state of the non-inverting pin/pad as referenced |* to the inverting pin/pad). For SPICE, Verilog-A(MS) or VHDL-A(MS) models, the A_to_D line | must name the A_signal port under either port1 or port2, as | with a single-ended buffer. Change the caption of Figure 8 from: | Figure 8 - Example SPICE implementation to: | Figure 8 - Example SPICE, Verilog-A(MS) or VHDL-A(MS) implementation Change the text above Figure 11 from: | The D_to_A or A_to_D adapters used for SPICE files may be set | up to control or respond to true differential ports. An | example is shown below. to: |* The D_to_A or A_to_D adapters used for SPICE, Verilog-A(MS) or VHDL-A(MS) files may be set | up to control or respond to true differential ports. An | example is shown below. Change the caption of Figure 11 from: | Figure 11: Example SPICE, Verilog-A(MS) or VHDL-A(MS) implementation of a true differential buffer In the 1st paragraph below Figure 11, replace: | If at-pad or at-pin measurement using a SPICE [External Model] | is desired, the vlow and vhigh entries under the A_to_D | subparameter must be consistent with the values of the [Diff | Pin] vdiff subparameter entry (the vlow value must match | -vdiff, and the vhigh value must match +vdiff). The logic with: |* If at-pad or at-pin measurement using a SPICE, Verilog-A(MS) or VHDL-A(MS) [External Model] | is desired, the vlow and vhigh entries under the A_to_D | subparameter must be consistent with the values of the [Diff | Pin] vdiff subparameter entry (the vlow value must match | -vdiff, and the vhigh value must match +vdiff). In the 2nd paragraph below Figure 11, replace: | IMPORTANT: For true-differential buffers under [External | Model], the user can choose whether to measure the analog | input response at the die pads or internal to the circuit | (this does not preclude tools from reporting digital D_receive | and/or analog responses in addition to at-pad A_signal | response). If at-pad measurements for a SPICE model are | desired, the A_signal_pos port would be named in the A_to_D | line under port1 and A_signal_neg under port2. with: | IMPORTANT: For true-differential buffers under [External | Model], the user can choose whether to measure the analog | input response at the die pads or internal to the circuit | (this does not preclude tools from reporting digital D_receive | and/or analog responses in addition to at-pad A_signal |* response). If at-pad measurements for a SPICE, Verilog-A(MS) or VHDL-A(MS) model are | desired, the A_signal_pos port would be named in the A_to_D | line under port1 and A_signal_neg under port2. In the 5th paragraph below Figure 11, replace: | For both SPICE and *-AMS true differential [External Model]s, | the EDA tool must not override or change the model author's | connection of the D_receive port. with: |* For SPICE, Verilog-A(MS) or VHDL-A(MS) and *-AMS true differential [External Model]s, | the EDA tool must not override or change the model author's | connection of the D_receive port. Under section "Series and Series Switch Models", replace: | As with other digital ports, the use of | SPICE in an [External Model] requires the user to declare | D_to_A ports, to convert the D_switch signal to an analog | input to the SPICE model (whether the port's state may | actually change during a simulation is determined by the EDA | tool used). with: | As with other digital ports, the use of |* SPICE, Verilog-A(MS) or VHDL-A(MS) in an [External Model] requires the user to declare | D_to_A ports, to convert the D_switch signal to an analog |* input to the SPICE, Verilog-A(MS) or VHDL-A(MS) model (whether the port's state may | actually change during a simulation is determined by the EDA | tool used). MAYBE: ====== Add an example for [External Model] using Verilog-A(MS) and/or VHDL-A(MS) Add an example for True Differential [External Model] using Verilog-A(MS) and/or VHDL-A(MS) Add an example for Pseudo Differential [External Model] using Verilog-A(MS) and/or VHDL-A(MS) Under the keywords [External Circuit], [End External Circuit], replace: | Language: | | Accepts "SPICE", "VHDL-AMS", or "Verilog-AMS" as arguments. | The Language subparameter is required and may appear only | once. with: | Language: | |* Accepts "SPICE", "VHDL-AMS", "Verilog-AMS", "VHDL-A(MS)" |* or "Verilog-A(MS)" as arguments. The Language subparameter | is required and must appear only once. In the "Digital-to-Analog/Analog-to-Digital Conversions" replace: | These subparameters define all digital-to-analog and | analog-to-digital converters needed to properly connect | digital signals with the analog ports of referenced external | SPICE models. These subparameters must be used when [External | Circuit] references a file written in the SPICE language. | They are not permitted with Verilog-AMS or VHDL-AMS external | files. with: | These subparameters define all digital-to-analog and | analog-to-digital converters needed to properly connect | digital signals with the analog ports of referenced external |* SPICE, Verilog-A(MS) or VHDL-A(MS) models. These subparameters must be used when [External |* Circuit] references a file written in the SPICE, Verilog-A(MS) or VHDL-A(MS) language. | They are not permitted with Verilog-AMS or VHDL-AMS external | files. Under section "D_to_A" replace: | As assumed in [Model] and [External Model], some interface | ports of [External Circuit]s expect digital input signals. As | SPICE models understand only analog signals, some conversion | from digital to analog format is required. with: | As assumed in [Model] and [External Model], some interface | ports of [External Circuit]s expect digital input signals. As |* SPICE, Verilog-A(MS) or VHDL-A(MS) models understand only analog signals, some conversion | from digital to analog format is required. A couple of paragraphs down in the same section also replace: | The port1 and port2 | entries hold the SPICE analog input port names across which | voltages are specified. with: | The port1 and port2 |* entries hold the SPICE, Verilog-A(MS) or VHDL-A(MS) analog input port names across which | voltages are specified. Under section "A_to_D" replace: | The A_to_D subparameter is used to generate a digital state | ('0', '1', or 'X') based on analog voltages from the SPICE | model or from the pad/pin. This allows an analog signal from | the external SPICE circuit to be read as a digital signal by | the simulation tool. with: | The A_to_D subparameter is used to generate a digital state |* ('0', '1', or 'X') based on analog voltages from the SPICE, Verilog-A(MS) or VHDL-A(MS) | model or from the pad/pin. This allows an analog signal from |* the external SPICE, Verilog-A(MS) or VHDL-A(MS) circuit to be read as a digital signal by | the simulation tool. A number of paragraphs down in the same section also replace: | Note that, while the port assignments and SPICE model data | must be provided by the user, the D_to_A and A_to_D converters | will be provided automatically by the tool. There is no need | for the user to develop external SPICE code specifically for | these functions. with: |* Note that, while the port assignments and SPICE, Verilog-A(MS) or VHDL-A(MS) model data | must be provided by the user, the D_to_A and A_to_D converters | will be provided automatically by the tool. There is no need |* for the user to develop external SPICE, Verilog-A(MS) or VHDL-A(MS) code specifically for | these functions. MAYBE: ====== Add an example for [External Circuit] using Verilog-A(MS) and/or VHDL-A(MS) Add an example for Interconnect Structure [External Circuit] using Verilog-A(MS) and/or VHDL-A(MS) ****************************************************************************** ANALYSIS PATH/DATA THAT LED TO SPECIFICATION Additional detail and/or specification changes may be required to make the BIRD fully compatible with the features and syntax of Section 6b. ***************************************************************************** ANY OTHER BACKGROUND INFORMATION: ******************************************************************************